Application Notes - CMP Process Development on Copper/Low-K Wafers
Optimum polishing conditions
were found on the CMP Tester mod. CP-4 for advanced wafers, with
efficient copper polishing without delamination of silicon carbide from
low-K material.
Samples used:
Experimental
Sematech wafers with the following structure:
Cu
on Ta on SiC on Low-K on Silicon (prepared by Jeffrey T. Wetzel, Program Manager for Low-K Dielectrics and Shin Kook Lee, CMP Program Manager)
Test Procedures and Parameters:
Bench-top CMP Tester mod. CP-4 was utilized with simultaneous real-time processing of micro-tribological information on the following signals:
-
normal load and friction force via proprietary sensors and amplifiers, which allows to measure dynamic coefficient of friction COF as their ratio;
-
contact high frequency acoustic emission AE via proprietary sensors and amplifiers.
Upper specimens: 2” wafer coupon, sliding laterally by 1” back and forth at 5 mm/sec, 4.25” conditioning disc, being rotated by a polishing pad.
Lower specimens: 6” polishing pads, rotating at constant speed.
Polishing slurry: continuous flow.
Observations :
Dependencies
of coefficient of friction (COF) and acoustic
emission signal (AE) at
different
loads and speeds for Low-K , SiC and Cu top layers are presented in
a summary table below.
COF
reflected contact conditions (rubbing or floating) and materials being
polished (0.40 for low-K, 0.55 for Cu),
AE
reflected regimes of material removal (<0.1 for floating, >1 with peaks for delamination, smooth curves for
polishing).
The
above data has allowed to determine the optimum CMP conditions, at the
highest polishing rate with no delamination, then confirmed by the data
presented in the document below.
Effect
of Speed on Copper/Low-K Polishing
Effect
of Pressure on Copper/Low-K Polishing
Repeatability
of AE data
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